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Chapter 4: Development Board Setup
4–3
Factory Default Switch Settings
Figure 4–2 shows the switch locations and the default position of each switch on the
bottom side of the board.
Figure 4–2. Switch Locations and Default Settings on the Board Bottom
J28
50
60
MAX
RLD_ZQ_IMPED
J29
DDR3_TEST_HDR
To restore the switches to their factory default settings, perform the following steps:
1. Set the PGM CONFIG SELECT rotary switch (SW5) to the 0 position, as shown in
Figure 4–1 .
2. Set DIP switch bank (SW1) to match Table 4–1 and Figure 4–1 .
Table 4–1. SW1 Dip Switch Settings (Part 1 of 2)
Switch
Board
Label
Function
Default
Position
Switch 1 has the following options:
1
CLK50_EN
■
When on, the 50 MHz clock is disabled.
Off
■
When off, the 50 MHz clock is enabled.
Switch 2 has the following options:
2
CLK66_EN
■
When on, the 66 MHz clock is disabled.
Off
■
When off, the 66 MHz clock is enabled.
June 2011
Altera Corporation
Stratix IV E FPGA Development Kit User Guide
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